EDN

Choose your PLL lock-time measurement

Rising clock speeds and tighter signal timing has increased demand for accurate high-frequency modules. The PLL (phase-locked loop), which generates a high-frequency output signal based on an input ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 3)

A special technique produces very wide loop BWs in high-frequency PLLs (and hence, indirect (PLL) synthesizers), thereby achieving very low phase noise rivaling that of direct (MMD) synthesizers. A ...
EDN

SOC-PLL design requires trade-offs

PLLs (phase-locked loops) are common analogcircuits in SOCs (systems on chips). Almost allSOCs with a clock rate greater than 30 MHzuse a PLL for frequency synthesis. However, a“one-size-fits-all” PLL ...
Design-Reuse

Silicon-Accurate Fractional-N PLL Design

Fractional-N PLLs are a useful class of PLLs and not well understood. This paper explains in simple terms how these differ from a regular integer PLL. Common applications are listed along with a brief ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 1)

This is Part 1 of a three-part series. As modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher performance than ever before, they’re ...