Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
Design-Reuse

Smart way to memory controller verification: Synopsys Memory VIP

Today verification team are facing contradicting pressure, at one end they are asked to reduce the verification schedule while at other end the design complexity is increasing. To overcome the ...
EDN

Implementing an all-digital PHY and delay-locked loop for high-speed DDR2/3 memory interfaces

A high-speed DDR2, DDR2/3, or DDR3 DRAM interface for off-chip memory provides a powerful tool to meet the high-performance demands of new electronic products. However, with advancements come new ...
Design-Reuse

Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions

Choosing the right type of memory is critical to ensure that the power and performance requirements are met for the target application. Memory technologies have significantly evolved over the last ...